This commit is contained in:
2024-12-24 01:17:09 -08:00
parent b620dd9718
commit 6d0b1ab194
2 changed files with 30 additions and 20 deletions

View File

@@ -30,22 +30,15 @@ struct Circuit : CustomStringConvertible {
func readInput(_ filePath: String) throws -> Circuit { func readInput(_ filePath: String) throws -> Circuit {
let content = try String(contentsOfFile: filePath, encoding: .ascii) let content = try String(contentsOfFile: filePath, encoding: .ascii)
let nodeRe = try Regex(#"([a-z0-9]+): (0|1)"#)
let gateRe = try Regex(#"([a-z0-9]+) (AND|OR|XOR) ([a-z0-9]+) -> ([a-z0-9]+)"#) let gateRe = try Regex(#"([a-z0-9]+) (AND|OR|XOR) ([a-z0-9]+) -> ([a-z0-9]+)"#)
let opMap: [String: Op] = [ let opMap: [String: Op] = [
"AND": { $0 && $1 }, "AND": { $0 && $1 },
"OR": { $0 || $1 }, "OR": { $0 || $1 },
"XOR": { $0 != $1 } "XOR": { $0 != $1 }
] ]
var nodes: [String: Bool] = [:]
var gates: [Gate] = [] var gates: [Gate] = []
var endNodes: Set<String> = [] var endNodes: Set<String> = []
for line in content.split(separator: "\n") { for line in content.split(separator: "\n") {
if let m = line.wholeMatch(of: nodeRe) {
let node = String(m.output[1].substring!)
let val = m.output[2].substring! == "1"
nodes[node] = val
}
if let m = line.wholeMatch(of: gateRe) { if let m = line.wholeMatch(of: gateRe) {
let in1 = String(m.output[1].substring!) let in1 = String(m.output[1].substring!)
let op = opMap[String(m.output[2].substring!)]! let op = opMap[String(m.output[2].substring!)]!
@@ -57,16 +50,29 @@ func readInput(_ filePath: String) throws -> Circuit {
} }
} }
} }
return Circuit(gates: gates, nodes: nodes, pendingEndNodes: endNodes) return Circuit(gates: gates, nodes: [:], pendingEndNodes: endNodes)
}
extension Int {
func toNodes(_ prefix: String) -> [String: Bool] {
var nodes: [String: Bool] = [:]
for i in (0..<45) {
nodes[prefix + String(format: "%02d", i)] = ((self >> i) & 1) == 1
}
return nodes
}
} }
var circuit = try readInput(CommandLine.arguments[1]) var circuit = try readInput(CommandLine.arguments[1])
// generate random x y to try
let x = Int.random(in: 0..<(1<<45))
let y = Int.random(in: 0..<(1<<45))
circuit.nodes.merge(x.toNodes("x")) { l, r in l }
circuit.nodes.merge(y.toNodes("y")) { l, r in l }
// just print out the wrong bits for manual debugging. See input.dot // just print out the wrong bits for manual debugging. See input.dot
// print(circuit)
while true { while true {
if let z = circuit.value(of: "z"), if let z = circuit.value(of: "z") {
let x = circuit.value(of: "x"),
let y = circuit.value(of: "y")
{
print("x: " + String(x, radix: 2).reversed()) print("x: " + String(x, radix: 2).reversed())
print("y: " + String(y, radix: 2).reversed()) print("y: " + String(y, radix: 2).reversed())
let zStr = String(z, radix: 2).reversed() let zStr = String(z, radix: 2).reversed()
@@ -82,3 +88,7 @@ while true {
circuit.run() circuit.run()
} }
// use graphviz to render input.dot to svg
// run program to find out first bit that failed (highlighted in red)
// look at svg around that for irregularities (regular full adders are obvious)
// in this case z16 <-> fkb and z31 <-> rdn

View File

@@ -109,7 +109,7 @@ rhk AND btv -> rmv
fjs XOR bmv -> z44 fjs XOR bmv -> z44
btv XOR rhk -> z25 btv XOR rhk -> z25
wgk OR ppp -> vnc wgk OR ppp -> vnc
kcm XOR grr -> fkb kcm XOR grr -> z16
fkb AND rcc -> fbb fkb AND rcc -> fbb
dbd XOR shb -> z15 dbd XOR shb -> z15
y38 XOR x38 -> vsq y38 XOR x38 -> vsq
@@ -145,7 +145,7 @@ x11 XOR y11 -> ftq
y04 XOR x04 -> mtb y04 XOR x04 -> mtb
vnm AND mgr -> phc vnm AND mgr -> phc
jfq OR tsw -> ksh jfq OR tsw -> ksh
gcg XOR nbm -> rrn gcg XOR nbm -> z37
wdv OR qph -> mcv wdv OR qph -> mcv
x19 AND y19 -> pdb x19 AND y19 -> pdb
rqf XOR hvv -> z21 rqf XOR hvv -> z21
@@ -169,17 +169,17 @@ y22 XOR x22 -> jck
tph AND hbk -> jhd tph AND hbk -> jhd
x34 AND y34 -> hrd x34 AND y34 -> hrd
ssf XOR hqr -> z19 ssf XOR hqr -> z19
y37 AND x37 -> z37 y37 AND x37 -> rrn
y04 AND x04 -> dgw y04 AND x04 -> dgw
qft AND twj -> qpn qft AND twj -> qpn
tnn OR bss -> z16 tnn OR bss -> fkb
x12 AND y12 -> ppp x12 AND y12 -> ppp
kmf OR cdb -> qnf kmf OR cdb -> qnf
vsq XOR jrg -> z38 vsq XOR jrg -> z38
ccs XOR rsj -> z29 ccs XOR rsj -> z29
y01 XOR x01 -> jnj y01 XOR x01 -> jnj
mtb XOR jdk -> z04 mtb XOR jdk -> z04
y21 AND x21 -> rqf y21 AND x21 -> nnr
hnq XOR dwd -> z18 hnq XOR dwd -> z18
x19 XOR y19 -> ssf x19 XOR y19 -> ssf
y34 XOR x34 -> hnk y34 XOR x34 -> hnk
@@ -188,7 +188,7 @@ x08 XOR y08 -> twj
fvc OR pkv -> thm fvc OR pkv -> thm
x41 AND y41 -> gtv x41 AND y41 -> gtv
x06 AND y06 -> qmr x06 AND y06 -> qmr
qsj AND tjk -> z31 qsj AND tjk -> rdn
vhj OR rrn -> jrg vhj OR rrn -> jrg
jrg AND vsq -> tkt jrg AND vsq -> tkt
y15 AND x15 -> svk y15 AND x15 -> svk
@@ -211,7 +211,7 @@ y32 AND x32 -> scw
dgr AND vnc -> jrk dgr AND vnc -> jrk
thm XOR dnf -> z43 thm XOR dnf -> z43
bgj OR chb -> qsj bgj OR chb -> qsj
qsj XOR tjk -> rdn qsj XOR tjk -> z31
thq OR knv -> rbk thq OR knv -> rbk
sqr AND njb -> smh sqr AND njb -> smh
x15 XOR y15 -> shb x15 XOR y15 -> shb
@@ -244,7 +244,7 @@ x13 XOR y13 -> dgr
jnj AND prt -> cdb jnj AND prt -> cdb
x10 XOR y10 -> vmf x10 XOR y10 -> vmf
y37 XOR x37 -> gcg y37 XOR x37 -> gcg
x21 XOR y21 -> nnr x21 XOR y21 -> rqf
qst XOR hbc -> z24 qst XOR hbc -> z24
rcm AND fjc -> pfb rcm AND fjc -> pfb
y18 AND x18 -> pnv y18 AND x18 -> pnv