mirror of
https://github.com/Candygoblen123/SwiftNES.git
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create Rom.swift and bus.swift
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parent
88d6a22bad
commit
915bff96a1
37
Sources/Bus.swift
Normal file
37
Sources/Bus.swift
Normal file
@ -0,0 +1,37 @@
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class Bus {
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var cpuVram: [UInt8] = .init(repeating: 0, count: 2048)
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fileprivate let RAM : UInt16 = 0x0000
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fileprivate let RAM_MIRRORS_END: UInt16 = 0x1FFF
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fileprivate let PPU_REGISTERS: UInt16 = 0x2000
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fileprivate let PPU_REGISTERS_MIRRORS_END: UInt16 = 0x3FFF
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}
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extension Bus: Memory {
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func memRead(_ addr: UInt16) -> UInt8 {
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switch addr {
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case RAM...RAM_MIRRORS_END:
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let mirrorDownAddr = addr & 0b00000111_11111111
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return self.cpuVram[Int(mirrorDownAddr)]
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case PPU_REGISTERS...PPU_REGISTERS_MIRRORS_END:
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let mirrorDownAddr = addr & 0b00100000_00000111;
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fatalError("PPU not implemented yet")
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default:
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print("Ignoring mem access at \(addr)")
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return 0
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}
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}
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func memWrite(_ addr: UInt16, data: UInt8) {
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switch addr {
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case RAM...RAM_MIRRORS_END:
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let mirrorDownAddr = addr & 0b11111111111
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self.cpuVram[Int(mirrorDownAddr)] = data
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case PPU_REGISTERS...PPU_REGISTERS_MIRRORS_END:
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let mirrorDownAddr = addr & 0b00100000_00000111
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fatalError("PPU is not implemented yet!")
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default:
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print("Ignorming mem-write at \(addr)")
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}
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}
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}
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@ -37,7 +37,7 @@ class CPU {
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var stackPointer: UInt8 = STACK_RESET
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var status: CPUFlags = [.interruptDisable, .break2]
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var programCounter: UInt16 = 0
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private var memory = [UInt8](repeating: 0, count: 0xFFFF)
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var bus = Bus()
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func getOpperandAddress(_ mode: AddressingMode) -> UInt16 {
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@ -98,7 +98,7 @@ class CPU {
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}
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func load(_ program: [UInt8]) {
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memory[0x0600 ..< (0x0600 + program.count)] = program[0..<program.count]
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//memory[0x0600 ..< (0x0600 + program.count)] = program[0..<program.count]
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memWriteU16(0xFFFC, data: 0x0600)
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}
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@ -108,7 +108,7 @@ class CPU {
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func run(onCycle: @escaping () -> (), onComplete: @escaping () -> ()) {
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let opcodes = OPCODES_MAP
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Timer.scheduledTimer(withTimeInterval: 0.00007, repeats: true) { [self] timer in
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_ = Timer.scheduledTimer(withTimeInterval: 0.00007, repeats: true) { [self] timer in
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processOpcodes(onCycle: onCycle, opcodes: opcodes, timer: timer) {
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onComplete()
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}
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@ -390,11 +390,19 @@ class CPU {
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extension CPU: Memory {
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func memRead(_ addr: UInt16) -> UInt8 {
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memory[Int(addr)]
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return bus.memRead(addr)
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}
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func memWrite(_ addr: UInt16, data: UInt8) {
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memory[Int(addr)] = data
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bus.memWrite(addr, data: data)
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}
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func memReadU16(_ addr: UInt16) -> UInt16 {
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return bus.memReadU16(addr)
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}
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func memWriteU16(_ addr: UInt16, data: UInt16) {
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bus.memWriteU16(addr, data: data)
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}
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}
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50
Sources/Rom.swift
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50
Sources/Rom.swift
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@ -0,0 +1,50 @@
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struct Rom {
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fileprivate let PRG_ROM_PAGE_SIZE = 16384
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fileprivate let CHR_ROM_PAGE_SIZE = 8192
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var program: [UInt8]
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var character: [UInt8]
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var mapper: UInt8
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var screenMirror: Mirroring
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init(_ raw: [UInt8]) throws {
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guard raw[0...4] == [0x4E, 0x45, 0x53, 0x1A] else { throw HeaderParseError.notINES("File is not in iNES file format.") }
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mapper = (raw[7] & 0b1111_0000) | (raw[6] >> 4)
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let inesVer = (raw[7] >> 2) & 0b11
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guard inesVer == 0 else { throw HeaderParseError.iNes2("iNES2.0 format not supported.") }
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let fourScreen = raw[6] & 0b1000 != 0
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let vertMirroring = raw[6] & 0b1 != 0
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screenMirror = switch (fourScreen, vertMirroring) {
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case (true, _):
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Mirroring.fourScreen
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case (false, true):
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Mirroring.vertical
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case (false, false):
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Mirroring.horizontal
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}
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let programSize = Int(raw[4]) * PRG_ROM_PAGE_SIZE
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let characterSize = Int(raw[5]) * CHR_ROM_PAGE_SIZE
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let skipTrainer = raw[6] & 0b100 != 0
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let programStart = 16 + (skipTrainer ? 512 : 0)
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let characterStart = programStart + programSize
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program = Array(raw[programStart...(programStart + programSize)])
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character = Array(raw[characterStart...(characterStart + characterSize)])
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}
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}
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enum Mirroring {
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case vertical
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case horizontal
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case fourScreen
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}
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enum HeaderParseError: Error {
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case notINES(String)
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case iNes2(String)
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}
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