mirror of
https://github.com/Candygoblen123/SwiftNES.git
synced 2024-09-18 16:41:01 -05:00
implement undocumented opcodes
This commit is contained in:
Andrew Glaze
parent
af72573d13
commit
5f770589c8
1
.gitignore
vendored
1
.gitignore
vendored
@ -8,3 +8,4 @@ DerivedData/
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.netrc
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*.nes
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*.log
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@ -37,46 +37,57 @@ class CPU {
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var stackPointer: UInt8 = STACK_RESET
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var status: CPUFlags = [.interruptDisable, .break2]
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var programCounter: UInt16 = 0
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var bus: Bus?
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var bus: Bus
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init(bus: Bus) {
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self.bus = bus
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}
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func getOpperandAddress(_ mode: AddressingMode) -> UInt16 {
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switch mode {
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case .Immediate:
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return programCounter
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default:
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return getAbsoluteAddress(mode, addr: programCounter)
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}
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}
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func getAbsoluteAddress(_ mode: AddressingMode, addr: UInt16) -> UInt16 {
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switch mode {
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case .ZeroPage:
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return UInt16(memRead(programCounter))
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return UInt16(memRead(addr))
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case .Absolute:
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return memReadU16(programCounter)
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return memReadU16(addr)
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case .ZeroPage_X:
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let pos = memRead(programCounter)
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let pos = memRead(addr)
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let addr = pos &+ register_x
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return UInt16(addr)
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case .ZeroPage_Y:
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let pos = memRead(programCounter)
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let pos = memRead(addr)
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let addr = pos &+ register_y
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return UInt16(addr)
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case .Absolute_X:
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let base = memReadU16(programCounter)
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let base = memReadU16(addr)
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return base &+ UInt16(register_x)
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case .Absolute_Y:
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let base = memReadU16(programCounter)
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let base = memReadU16(addr)
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return base &+ UInt16(register_y)
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case .Indirect_X:
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let base = memRead(programCounter)
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let base = memRead(addr)
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let ptr = UInt8(base) &+ register_x
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let lo = memRead(UInt16(ptr))
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let hi = memRead(UInt16(ptr &+ 1))
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return UInt16(hi) << 8 | UInt16(lo)
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case .Indirect_Y:
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let base = memRead(programCounter)
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let base = memRead(addr)
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let lo = memRead(UInt16(base))
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let hi = memRead(UInt16(base &+ 1))
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let deref_base = UInt16(hi) << 8 | UInt16(lo)
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let deref = deref_base &+ UInt16(register_y)
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return deref
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case .NoneAddressing:
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default:
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fatalError("mode \(mode) is not implemented")
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}
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}
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@ -91,17 +102,21 @@ class CPU {
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programCounter = self.memReadU16(0xFFFC)
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}
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func loadAndRun(_ program: [UInt8]) {
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load(program)
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reset()
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run()
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}
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//func loadAndRun(_ program: [UInt8]) {
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//load(program)
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//reset()
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//run()
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//}
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func load(_ program: [UInt8]) {
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//func load(_ program: [UInt8]) {
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//bus = Bus(try! Rom(program))
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//for i in 0..<program.count {
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//memWrite(0x8000 + UInt16(i), data: program[i])
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//}
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//memory[0x0600 ..< (0x0600 + program.count)] = program[0..<program.count]
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bus = Bus(try! Rom(program))
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memWriteU16(0xFFFC, data: 0x0600)
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}
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//memWriteU16(0xFFFC, data: 0x0600)
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//}
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func run() {
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run(onCycle: {}, onComplete: {})
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@ -208,7 +223,7 @@ class CPU {
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let indirectRef: UInt16
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if memAddr & 0x00ff == 0x00ff {
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let lo = memRead(memAddr)
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let hi = memRead(memAddr & 0x00ff)
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let hi = memRead(memAddr & 0xff00)
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indirectRef = UInt16(hi) << 8 | UInt16(lo)
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} else {
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indirectRef = memReadU16(memAddr)
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@ -225,7 +240,7 @@ class CPU {
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case 0x40:
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status.rawValue = stackPop()
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status.remove(.break1)
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status.remove(.break2)
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status.insert(.break2)
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programCounter = stackPopU16()
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case 0xd0:
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@ -259,7 +274,7 @@ class CPU {
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case 0xea:
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return
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case 0xa8:
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register_y = register_x
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register_y = register_a
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updateZeroAndNegativeFlags(register_y)
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case 0xba:
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register_x = stackPointer
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@ -282,6 +297,67 @@ class CPU {
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case 0x00:
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timer.invalidate()
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onComplete()
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/// NOP Read
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case 0x04, 0x44, 0x64, 0x14, 0x34, 0x54, 0x74, 0xd4, 0xf4, 0x0c, 0x1c, 0x3c, 0x5c, 0x7c, 0xdc, 0xfc:
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let addr = getOpperandAddress(opcode.mode)
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let _ = self.memRead(addr)
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// Do nothing
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/// NOP
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case 0x1a, 0x3a, 0x5a, 0x7a, 0xda, 0xfa:
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{ /* Do Nothing */}()
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/// RRA
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case 0x67, 0x77, 0x6f, 0x7f, 0x7b, 0x63, 0x73:
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let data = ror(opcode.mode)
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addToRegisterA(data)
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/// ISB
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case 0xe7, 0xf7, 0xef, 0xff, 0xfb, 0xe3, 0xf3:
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let data = inc(opcode.mode)
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subFromRegisterA(data)
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/// SKB
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case 0x80, 0x82, 0x89, 0xc2, 0xe2:
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{ /* 2 byte NOP immediate, do nothing */ }()
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/// LAX
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case 0xa7, 0xb7, 0xaf, 0xbf, 0xa3, 0xb3:
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let addr = getOpperandAddress(opcode.mode)
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let data = memRead(addr)
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setRegisterA(data)
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register_x = register_a
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/// SAX
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case 0x87, 0x97, 0x8f, 0x83:
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let data = register_a & register_x
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let addr = getOpperandAddress(opcode.mode)
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memWrite(addr, data: data)
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// Unoffical SBC
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case 0xeb:
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let addr = getOpperandAddress(opcode.mode)
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let data = self.memRead(addr)
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subFromRegisterA(data)
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/// DCP
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case 0xc7, 0xd7, 0xCF, 0xdF, 0xdb, 0xd3, 0xc3:
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let addr = getOpperandAddress(opcode.mode)
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var data = memRead(addr)
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data = data &- 1
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memWrite(addr, data: data)
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if data <= register_a {
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status.insert(.carry)
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}
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let tmp = register_a &- data
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updateZeroAndNegativeFlags(tmp)
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/// SLO
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case 0x07, 0x17, 0x0F, 0x1f, 0x1b, 0x03, 0x13:
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let data = asl(opcode.mode)
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orWithRegisterA(data)
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/// RLA
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case 0x27, 0x37, 0x2F, 0x3F, 0x3b, 0x33, 0x23:
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let data = rol(opcode.mode)
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andWithRegisterA(data)
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/// SRE
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case 0x47, 0x57, 0x4F, 0x5f, 0x5b, 0x43, 0x53:
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let data = lsr(opcode.mode)
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xorWithRegisterA(data)
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default: fatalError("TODO!")
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}
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@ -342,6 +418,22 @@ class CPU {
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setRegisterA(result)
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}
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func subFromRegisterA(_ data: UInt8) {
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addToRegisterA(UInt8(bitPattern: (Int8(bitPattern: data) &* -1) &- 1))
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}
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func orWithRegisterA(_ data: UInt8) {
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setRegisterA(data | self.register_a)
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}
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func xorWithRegisterA(_ data: UInt8) {
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setRegisterA(data ^ self.register_a)
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}
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func andWithRegisterA(_ data: UInt8) {
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setRegisterA(data & register_a)
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}
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func stackPop() -> UInt8 {
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stackPointer = stackPointer &+ 1
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return memRead(STACK + UInt16(stackPointer))
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@ -391,19 +483,19 @@ class CPU {
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extension CPU: Memory {
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func memRead(_ addr: UInt16) -> UInt8 {
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return bus!.memRead(addr)
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return bus.memRead(addr)
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}
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func memWrite(_ addr: UInt16, data: UInt8) {
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bus!.memWrite(addr, data: data)
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bus.memWrite(addr, data: data)
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}
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func memReadU16(_ addr: UInt16) -> UInt16 {
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return bus!.memReadU16(addr)
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return bus.memReadU16(addr)
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}
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func memWriteU16(_ addr: UInt16, data: UInt16) {
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bus!.memWriteU16(addr, data: data)
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bus.memWriteU16(addr, data: data)
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}
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}
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@ -227,7 +227,7 @@ extension CPU {
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func plp() {
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status.rawValue = stackPop()
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status.remove(.break1)
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status.remove(.break2)
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status.insert(.break2)
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}
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func php() {
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107
Sources/Trace.swift
Normal file
107
Sources/Trace.swift
Normal file
@ -0,0 +1,107 @@
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func dumpCpuState(_ cpu: CPU) -> String {
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guard let opcode = OPCODES_MAP[cpu.memRead(cpu.programCounter)] else { fatalError("Not an opcode: \(cpu.memRead(cpu.programCounter))") }
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var hexOpcode = [String(format: "%02X", cpu.memRead(cpu.programCounter))]
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let (memAddr, storedVal) = switch opcode.mode {
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case .Immediate, .NoneAddressing:
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(UInt16(0), UInt8(0))
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default:
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{
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let addr = cpu.getAbsoluteAddress(opcode.mode, addr: cpu.programCounter + 1)
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return (addr, cpu.memRead(addr))
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}()
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}
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let operand = switch opcode.len {
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case 1:
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{
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return switch opcode.code {
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case 0x0a, 0x4a, 0x2a, 0x6a:
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"A "
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default:
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""
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}
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}()
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case 2:
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{
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let address = cpu.memRead(cpu.programCounter + 1)
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hexOpcode.append(String(format: "%02X", address))
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return switch opcode.mode {
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case .Immediate:
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String(format: "#$%02X", address)
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case .ZeroPage:
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String(format: "$%02X = %02X", memAddr, storedVal)
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case .ZeroPage_X:
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String(format: "$%02X,X @ %02X = %02X", address, memAddr, storedVal)
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case .ZeroPage_Y:
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String(format: "$%02X,Y @ %02X = %02X", address, memAddr, storedVal)
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case .Indirect_X:
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String(format: "($%02X,X) @ %02X = %04X = %02X", address, address &+ cpu.register_x, memAddr, storedVal)
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case .Indirect_Y:
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String(format: "($%02X),Y = %04X @ %04X = %02X", address, memAddr &- UInt16(cpu.register_y), memAddr, storedVal)
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case .NoneAddressing:
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String(format: "$%04X", Int(cpu.programCounter) + 2 &+ Int(Int8(bitPattern: address)))
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default:
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fatalError("Unexpected addressing mode \(opcode.mode) has ops-length of 2. code: \(opcode.mnemonic)")
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}
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}()
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case 3:
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{
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let addressLo = cpu.memRead(cpu.programCounter + 1)
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let addressHi = cpu.memRead(cpu.programCounter + 2)
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hexOpcode.append(String(format: "%02X", addressLo))
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hexOpcode.append(String(format: "%02X", addressHi))
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let address = cpu.memReadU16(cpu.programCounter + 1)
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return switch opcode.mode {
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case .NoneAddressing:
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{
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// jmp indirect
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if (opcode.code == 0x6c) {
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let jmpAddr = if address & 0x00FF == 0x00FF {
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{
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let lo = cpu.memRead(address)
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let hi = cpu.memRead(address & 0xFF00)
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return UInt16(hi) << 8 | UInt16(lo)
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}()
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} else {
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cpu.memReadU16(address)
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}
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return String(format: "($%04X) = %04X", address, jmpAddr)
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} else {
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return String(format: "$%04X", address)
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}
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}()
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case .Absolute:
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String(format: "$%04X = %02X", memAddr, storedVal)
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case .Absolute_X:
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String(format: "$%04X,X @ %04X = %02X", address, memAddr, storedVal)
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case .Absolute_Y:
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String(format: "$%04X,Y @ %04X = %02X", address, memAddr, storedVal)
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default:
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fatalError("Unexpected addressing mode \(opcode.mode) has ops-length of 3. code: \(opcode.mnemonic)")
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}
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}()
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default:
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""
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}
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let hexString = hexOpcode.joined(separator: " ").padding(toLength: 8, withPad: " ", startingAt: 0)
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let asm = "\(String(format: "%04X", cpu.programCounter)) \(hexString) \(opcode.mnemonic.leftPadding(toLength: 4, withPad: " ")) \(operand)".padding(toLength: 47, withPad: " ", startingAt: 0)
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return String(format: "\(asm) A:%02X X:%02X Y:%02X P:%02X SP:%02X", cpu.register_a, cpu.register_x, cpu.register_y, cpu.status.rawValue, cpu.stackPointer)
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}
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extension String {
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func leftPadding(toLength: Int, withPad character: Character) -> String {
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let stringLength = self.count
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if stringLength < toLength {
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return String(repeatElement(character, count: toLength - stringLength)) + self
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} else {
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return String(self.suffix(toLength))
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}
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}
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}
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@ -94,21 +94,23 @@ func readScreenState(_ cpu: CPU, frame: inout [UInt8]) -> Bool {
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return update
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}
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guard let rom = NSData(contentsOfFile: "snake.nes") else { fatalError("Rom not found") }
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guard let rom = NSData(contentsOfFile: "nestest.nes") else { fatalError("Rom not found") }
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var gameCode = [UInt8](repeating: 0, count: rom.length)
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rom.getBytes(&gameCode, length: rom.length)
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let bus = Bus(try! Rom(gameCode))
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var cpu = CPU()
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cpu.load(gameCode)
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var cpu = CPU(bus: bus)
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//cpu.load(gameCode)
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cpu.reset()
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cpu.programCounter = 0xC000
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var screenState = [UInt8](repeating: 0, count: 32 * 3 * 32)
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var rng = SystemRandomNumberGenerator()
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cpu.run(onCycle: {
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print(dumpCpuState(cpu))
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handleUserInput(cpu, event: &event)
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cpu.memWrite(0xfe, data: UInt8.random(in: 1...16, using: &rng))
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//cpu.memWrite(0xfe, data: UInt8.random(in: 1...16, using: &rng))
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if readScreenState(cpu, frame: &screenState) {
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SDL_UpdateTexture(texture, nil, screenState, 32 * 3)
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@ -16,7 +16,7 @@ let CPU_OP_CODES: [OpCode] = [
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OpCode(code: 0x75, mnemonic: "ADC", len: 2, cycles: 4, mode: .ZeroPage_X),
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OpCode(code: 0x6d, mnemonic: "ADC", len: 3, cycles: 4, mode: .Absolute),
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OpCode(code: 0x7d, mnemonic: "ADC", len: 3, cycles: 4 /* +1 if page crossed */, mode: .Absolute_X),
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OpCode(code: 0x79, mnemonic: "ADC", len: 2, cycles: 5 /* +1 if page crossed */, mode: .Absolute_Y),
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OpCode(code: 0x79, mnemonic: "ADC", len: 3, cycles: 5 /* +1 if page crossed */, mode: .Absolute_Y),
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OpCode(code: 0x61, mnemonic: "ADC", len: 2, cycles: 5, mode: .Indirect_X),
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OpCode(code: 0x71, mnemonic: "ADC", len: 2, cycles: 5 /* +1 if page crossed */, mode: .Indirect_Y),
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@ -165,11 +165,11 @@ let CPU_OP_CODES: [OpCode] = [
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OpCode(code: 0x91, mnemonic: "STA", len: 2, cycles: 6, mode: .Indirect_Y),
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OpCode(code: 0x86, mnemonic: "STX", len: 2, cycles: 3, mode: .ZeroPage),
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OpCode(code: 0x96, mnemonic: "STX", len: 2, cycles: 4, mode: .Absolute_Y),
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OpCode(code: 0x96, mnemonic: "STX", len: 2, cycles: 4, mode: .ZeroPage_Y),
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OpCode(code: 0x8e, mnemonic: "STX", len: 3, cycles: 4, mode: .Absolute),
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OpCode(code: 0x84, mnemonic: "STY", len: 2, cycles: 3, mode: .ZeroPage),
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OpCode(code: 0x94, mnemonic: "STY", len: 2, cycles: 4, mode: .Absolute_X),
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OpCode(code: 0x94, mnemonic: "STY", len: 2, cycles: 4, mode: .ZeroPage_X),
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OpCode(code: 0x8c, mnemonic: "STY", len: 3, cycles: 4, mode: .Absolute),
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/// Flag Clears
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@ -193,6 +193,135 @@ let CPU_OP_CODES: [OpCode] = [
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OpCode(code: 0x68, mnemonic: "PLA", len: 1, cycles: 4, mode: .NoneAddressing),
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OpCode(code: 0x08, mnemonic: "PHP", len: 1, cycles: 3, mode: .NoneAddressing),
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OpCode(code: 0x28, mnemonic: "PLP", len: 1, cycles: 4, mode: .NoneAddressing),
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/// Undocumented
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|
||||
OpCode(code: 0xc7, mnemonic: "*DCP", len: 2, cycles: 5, mode: .ZeroPage),
|
||||
OpCode(code: 0xd7, mnemonic: "*DCP", len: 2, cycles: 6, mode: .ZeroPage_X),
|
||||
OpCode(code: 0xCF, mnemonic: "*DCP", len: 3, cycles: 6, mode: .Absolute),
|
||||
OpCode(code: 0xdF, mnemonic: "*DCP", len: 3, cycles: 7, mode: .Absolute_X),
|
||||
OpCode(code: 0xdb, mnemonic: "*DCP", len: 3, cycles: 7, mode: .Absolute_Y),
|
||||
OpCode(code: 0xd3, mnemonic: "*DCP", len: 2, cycles: 8, mode: .Indirect_Y),
|
||||
OpCode(code: 0xc3, mnemonic: "*DCP", len: 2, cycles: 8, mode: .Indirect_X),
|
||||
|
||||
|
||||
OpCode(code: 0x27, mnemonic: "*RLA", len: 2, cycles: 5, mode: .ZeroPage),
|
||||
OpCode(code: 0x37, mnemonic: "*RLA", len: 2, cycles: 6, mode: .ZeroPage_X),
|
||||
OpCode(code: 0x2F, mnemonic: "*RLA", len: 3, cycles: 6, mode: .Absolute),
|
||||
OpCode(code: 0x3F, mnemonic: "*RLA", len: 3, cycles: 7, mode: .Absolute_X),
|
||||
OpCode(code: 0x3b, mnemonic: "*RLA", len: 3, cycles: 7, mode: .Absolute_Y),
|
||||
OpCode(code: 0x33, mnemonic: "*RLA", len: 2, cycles: 8, mode: .Indirect_Y),
|
||||
OpCode(code: 0x23, mnemonic: "*RLA", len: 2, cycles: 8, mode: .Indirect_X),
|
||||
|
||||
OpCode(code: 0x07, mnemonic: "*SLO", len: 2, cycles: 5, mode: .ZeroPage),
|
||||
OpCode(code: 0x17, mnemonic: "*SLO", len: 2, cycles: 6, mode: .ZeroPage_X),
|
||||
OpCode(code: 0x0F, mnemonic: "*SLO", len: 3, cycles: 6, mode: .Absolute),
|
||||
OpCode(code: 0x1f, mnemonic: "*SLO", len: 3, cycles: 7, mode: .Absolute_X),
|
||||
OpCode(code: 0x1b, mnemonic: "*SLO", len: 3, cycles: 7, mode: .Absolute_Y),
|
||||
OpCode(code: 0x03, mnemonic: "*SLO", len: 2, cycles: 8, mode: .Indirect_X),
|
||||
OpCode(code: 0x13, mnemonic: "*SLO", len: 2, cycles: 8, mode: .Indirect_Y),
|
||||
|
||||
OpCode(code: 0x47, mnemonic: "*SRE", len: 2, cycles: 5, mode: .ZeroPage),
|
||||
OpCode(code: 0x57, mnemonic: "*SRE", len: 2, cycles: 6, mode: .ZeroPage_X),
|
||||
OpCode(code: 0x4F, mnemonic: "*SRE", len: 3, cycles: 6, mode: .Absolute),
|
||||
OpCode(code: 0x5f, mnemonic: "*SRE", len: 3, cycles: 7, mode: .Absolute_X),
|
||||
OpCode(code: 0x5b, mnemonic: "*SRE", len: 3, cycles: 7, mode: .Absolute_Y),
|
||||
OpCode(code: 0x43, mnemonic: "*SRE", len: 2, cycles: 8, mode: .Indirect_X),
|
||||
OpCode(code: 0x53, mnemonic: "*SRE", len: 2, cycles: 8, mode: .Indirect_Y),
|
||||
|
||||
|
||||
OpCode(code: 0x80, mnemonic: "*NOP", len: 2, cycles: 2, mode: .Immediate),
|
||||
OpCode(code: 0x82, mnemonic: "*NOP", len: 2, cycles: 2, mode: .Immediate),
|
||||
OpCode(code: 0x89, mnemonic: "*NOP", len: 2, cycles: 2, mode: .Immediate),
|
||||
OpCode(code: 0xc2, mnemonic: "*NOP", len: 2, cycles: 2, mode: .Immediate),
|
||||
OpCode(code: 0xe2, mnemonic: "*NOP", len: 2, cycles: 2, mode: .Immediate),
|
||||
|
||||
|
||||
OpCode(code: 0xCB, mnemonic: "*AXS", len: 2, cycles: 2, mode: .Immediate),
|
||||
|
||||
OpCode(code: 0x6B, mnemonic: "*ARR", len: 2, cycles: 2, mode: .Immediate),
|
||||
|
||||
OpCode(code: 0xeb, mnemonic: "*SBC", len: 2, cycles: 2, mode: .Immediate),
|
||||
|
||||
OpCode(code: 0x0b, mnemonic: "*ANC", len: 2, cycles: 2, mode: .Immediate),
|
||||
OpCode(code: 0x2b, mnemonic: "*ANC", len: 2, cycles: 2, mode: .Immediate),
|
||||
|
||||
OpCode(code: 0x4b, mnemonic: "*ALR", len: 2, cycles: 2, mode: .Immediate),
|
||||
|
||||
OpCode(code: 0x04, mnemonic: "*NOP", len: 2, cycles: 3, mode: .ZeroPage),
|
||||
OpCode(code: 0x44, mnemonic: "*NOP", len: 2, cycles: 3, mode: .ZeroPage),
|
||||
OpCode(code: 0x64, mnemonic: "*NOP", len: 2, cycles: 3, mode: .ZeroPage),
|
||||
OpCode(code: 0x14, mnemonic: "*NOP", len: 2, cycles: 4, mode: .ZeroPage_X),
|
||||
OpCode(code: 0x34, mnemonic: "*NOP", len: 2, cycles: 4, mode: .ZeroPage_X),
|
||||
OpCode(code: 0x54, mnemonic: "*NOP", len: 2, cycles: 4, mode: .ZeroPage_X),
|
||||
OpCode(code: 0x74, mnemonic: "*NOP", len: 2, cycles: 4, mode: .ZeroPage_X),
|
||||
OpCode(code: 0xd4, mnemonic: "*NOP", len: 2, cycles: 4, mode: .ZeroPage_X),
|
||||
OpCode(code: 0xf4, mnemonic: "*NOP", len: 2, cycles: 4, mode: .ZeroPage_X),
|
||||
OpCode(code: 0x0c, mnemonic: "*NOP", len: 3, cycles: 4, mode: .Absolute),
|
||||
OpCode(code: 0x1c, mnemonic: "*NOP", len: 3, cycles: 4, mode: .Absolute_X),
|
||||
OpCode(code: 0x3c, mnemonic: "*NOP", len: 3, cycles: 4, mode: .Absolute_X),
|
||||
OpCode(code: 0x5c, mnemonic: "*NOP", len: 3, cycles: 4, mode: .Absolute_X),
|
||||
OpCode(code: 0x7c, mnemonic: "*NOP", len: 3, cycles: 4, mode: .Absolute_X),
|
||||
OpCode(code: 0xdc, mnemonic: "*NOP", len: 3, cycles: 4, mode: .Absolute_X),
|
||||
OpCode(code: 0xfc, mnemonic: "*NOP", len: 3, cycles: 4, mode: .Absolute_X),
|
||||
|
||||
OpCode(code: 0x67, mnemonic: "*RRA", len: 2, cycles: 5, mode: .ZeroPage),
|
||||
OpCode(code: 0x77, mnemonic: "*RRA", len: 2, cycles: 6, mode: .ZeroPage_X),
|
||||
OpCode(code: 0x6f, mnemonic: "*RRA", len: 3, cycles: 6, mode: .Absolute),
|
||||
OpCode(code: 0x7f, mnemonic: "*RRA", len: 3, cycles: 7, mode: .Absolute_X),
|
||||
OpCode(code: 0x7b, mnemonic: "*RRA", len: 3, cycles: 7, mode: .Absolute_Y),
|
||||
OpCode(code: 0x63, mnemonic: "*RRA", len: 2, cycles: 8, mode: .Indirect_X),
|
||||
OpCode(code: 0x73, mnemonic: "*RRA", len: 2, cycles: 8, mode: .Indirect_Y),
|
||||
|
||||
|
||||
OpCode(code: 0xe7, mnemonic: "*ISB", len: 2, cycles: 5, mode: .ZeroPage),
|
||||
OpCode(code: 0xf7, mnemonic: "*ISB", len: 2, cycles: 6, mode: .ZeroPage_X),
|
||||
OpCode(code: 0xef, mnemonic: "*ISB", len: 3, cycles: 6, mode: .Absolute),
|
||||
OpCode(code: 0xff, mnemonic: "*ISB", len: 3, cycles: 7, mode: .Absolute_X),
|
||||
OpCode(code: 0xfb, mnemonic: "*ISB", len: 3, cycles: 7, mode: .Absolute_Y),
|
||||
OpCode(code: 0xe3, mnemonic: "*ISB", len: 2, cycles: 8, mode: .Indirect_X),
|
||||
OpCode(code: 0xf3, mnemonic: "*ISB", len: 2, cycles: 8, mode: .Indirect_Y),
|
||||
|
||||
OpCode(code: 0x02, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x12, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x22, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x32, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x42, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x52, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x62, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x72, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x92, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0xb2, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0xd2, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0xf2, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
|
||||
OpCode(code: 0x1a, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x3a, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x5a, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0x7a, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0xda, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
OpCode(code: 0xfa, mnemonic: "*NOP", len: 1, cycles: 2, mode: .NoneAddressing),
|
||||
|
||||
OpCode(code: 0xab, mnemonic: "*LXA", len: 2, cycles: 3, mode: .Immediate), //todo: highly unstable and not used
|
||||
OpCode(code: 0x8b, mnemonic: "*XAA", len: 2, cycles: 3, mode: .Immediate), //todo: highly unstable and not used
|
||||
OpCode(code: 0xbb, mnemonic: "*LAS", len: 3, cycles: 2, mode: .Absolute_Y), //todo: highly unstable and not used
|
||||
OpCode(code: 0x9b, mnemonic: "*TAS", len: 3, cycles: 2, mode: .Absolute_Y), //todo: highly unstable and not used
|
||||
OpCode(code: 0x93, mnemonic: "*AHX", len: 2, cycles: 8, mode: .Indirect_Y), //todo: highly unstable and not used
|
||||
OpCode(code: 0x9f, mnemonic: "*AHX", len: 3, cycles: 4, mode: .Absolute_Y), //todo: highly unstable and not used
|
||||
OpCode(code: 0x9e, mnemonic: "*SHX", len: 3, cycles: 4, mode: .Absolute_Y), //todo: highly unstable and not used
|
||||
OpCode(code: 0x9c, mnemonic: "*SHY", len: 3, cycles: 4, mode: .Absolute_X), //todo: highly unstable and not used
|
||||
|
||||
OpCode(code: 0xa7, mnemonic: "*LAX", len: 2, cycles: 3, mode: .ZeroPage),
|
||||
OpCode(code: 0xb7, mnemonic: "*LAX", len: 2, cycles: 4, mode: .ZeroPage_Y),
|
||||
OpCode(code: 0xaf, mnemonic: "*LAX", len: 3, cycles: 4, mode: .Absolute),
|
||||
OpCode(code: 0xbf, mnemonic: "*LAX", len: 3, cycles: 4, mode: .Absolute_Y),
|
||||
OpCode(code: 0xa3, mnemonic: "*LAX", len: 2, cycles: 6, mode: .Indirect_X),
|
||||
OpCode(code: 0xb3, mnemonic: "*LAX", len: 2, cycles: 5, mode: .Indirect_Y),
|
||||
|
||||
OpCode(code: 0x87, mnemonic: "*SAX", len: 2, cycles: 3, mode: .ZeroPage),
|
||||
OpCode(code: 0x97, mnemonic: "*SAX", len: 2, cycles: 4, mode: .ZeroPage_Y),
|
||||
OpCode(code: 0x8f, mnemonic: "*SAX", len: 3, cycles: 4, mode: .Absolute),
|
||||
OpCode(code: 0x83, mnemonic: "*SAX", len: 2, cycles: 6, mode: .Indirect_X),
|
||||
]
|
||||
|
||||
let OPCODES_MAP: [UInt8: OpCode] = {
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
import XCTest
|
||||
@testable import SwiftNES
|
||||
|
||||
/*
|
||||
class CPUTests: XCTestCase {
|
||||
func test_lda() {
|
||||
let cpu = CPU()
|
||||
@ -364,3 +365,4 @@ extension CPU {
|
||||
expect.wait(sender)
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
71
Tests/TestRom.swift
Normal file
71
Tests/TestRom.swift
Normal file
@ -0,0 +1,71 @@
|
||||
import XCTest
|
||||
@testable import SwiftNES
|
||||
|
||||
class TestRom: XCTestCase {
|
||||
func testFormatTrace() {
|
||||
let expect = XCTestExpectation()
|
||||
let bus = Bus(try! Rom(getRom()))
|
||||
bus.memWrite(100, data: 0xa2)
|
||||
bus.memWrite(101, data: 0x01)
|
||||
bus.memWrite(102, data: 0xca)
|
||||
bus.memWrite(103, data: 0x88)
|
||||
bus.memWrite(104, data: 0x00)
|
||||
let cpu = CPU(bus: bus)
|
||||
cpu.programCounter = 0x64
|
||||
cpu.register_a = 1
|
||||
cpu.register_x = 2
|
||||
cpu.register_y = 3
|
||||
|
||||
var result: [String] = []
|
||||
cpu.run(
|
||||
onCycle: { result.append(dumpCpuState(cpu)) },
|
||||
onComplete: { expect.fulfill() }
|
||||
)
|
||||
wait(for: [expect], timeout: 0.5)
|
||||
XCTAssertEqual(
|
||||
"0064 A2 01 LDX #$01 A:01 X:02 Y:03 P:24 SP:FD",
|
||||
result[0]
|
||||
)
|
||||
XCTAssertEqual(
|
||||
"0066 CA DEX A:01 X:01 Y:03 P:24 SP:FD",
|
||||
result[1]
|
||||
)
|
||||
XCTAssertEqual(
|
||||
"0067 88 DEY A:01 X:00 Y:03 P:26 SP:FD",
|
||||
result[2]
|
||||
)
|
||||
}
|
||||
|
||||
func testFormatMemAccess() {
|
||||
let expect = XCTestExpectation()
|
||||
let bus = Bus(try! Rom(getRom()))
|
||||
bus.memWrite(100, data: 0x11)
|
||||
bus.memWrite(101, data: 0x33
|
||||
)
|
||||
bus.memWrite(0x33, data: 00)
|
||||
bus.memWrite(0x34, data: 04)
|
||||
|
||||
bus.memWrite(0x400, data: 0xAA)
|
||||
let cpu = CPU(bus: bus)
|
||||
cpu.programCounter = 0x64
|
||||
cpu.register_y = 0
|
||||
|
||||
var result: [String] = []
|
||||
cpu.run(
|
||||
onCycle: { result.append(dumpCpuState(cpu)) },
|
||||
onComplete: { expect.fulfill() }
|
||||
)
|
||||
wait(for: [expect], timeout: 0.5)
|
||||
XCTAssertEqual(
|
||||
"0064 11 33 ORA ($33),Y = 0400 @ 0400 = AA A:00 X:00 Y:00 P:24 SP:FD",
|
||||
result[0]
|
||||
)
|
||||
}
|
||||
|
||||
func getRom() -> [UInt8] {
|
||||
guard let rom = NSData(contentsOfFile: "nestest.nes") else { fatalError("Rom not found") }
|
||||
var gameCode = [UInt8](repeating: 0, count: rom.length)
|
||||
rom.getBytes(&gameCode, length: rom.length)
|
||||
return gameCode;
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user