mirror of
https://github.com/Candygoblen123/SwiftNES.git
synced 2024-11-09 14:36:24 -06:00
add LDA, STA, TAX, INX, BRK
This commit is contained in:
commit
f0b3dcd95b
8
.gitignore
vendored
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8
.gitignore
vendored
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.DS_Store
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/.build
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/Packages
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xcuserdata/
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DerivedData/
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.swiftpm/configuration/registries.json
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.swiftpm/xcode/package.xcworkspace/contents.xcworkspacedata
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.netrc
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15
Package.swift
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15
Package.swift
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// swift-tools-version: 5.9
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// The swift-tools-version declares the minimum version of Swift required to build this package.
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import PackageDescription
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let package = Package(
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name: "SwiftNES",
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targets: [
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// Targets are the basic building blocks of a package, defining a module or a test suite.
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// Targets can depend on other targets in this package and products from dependencies.
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.executableTarget(
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name: "SwiftNES"),
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.testTarget(name: "SwiftNESTests", dependencies: ["SwiftNES"])
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]
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)
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182
Sources/CPU.swift
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182
Sources/CPU.swift
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enum AddressingMode {
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case Immediate
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case ZeroPage
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case ZeroPage_X
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case ZeroPage_Y
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case Absolute
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case Absolute_X
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case Absolute_Y
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case Indirect_X
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case Indirect_Y
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case NoneAddressing
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}
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class CPU {
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var register_a: UInt8 = 0
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var register_x: UInt8 = 0
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var register_y: UInt8 = 0
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var status: UInt8 = 0
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var programCounter: UInt16 = 0
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private var memory = [UInt8](repeating: 0, count: 0xFFFF)
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func getOpperandAddress(_ mode: AddressingMode) -> UInt16 {
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switch mode {
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case .Immediate:
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return programCounter
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case .ZeroPage:
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return UInt16(memRead(programCounter))
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case .Absolute:
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return memReadU16(programCounter)
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case .ZeroPage_X:
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let pos = memRead(programCounter)
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let addr = pos &+ register_x
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return UInt16(addr)
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case .ZeroPage_Y:
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let pos = memRead(programCounter)
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let addr = pos &+ register_y
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return UInt16(addr)
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case .Absolute_X:
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let base = memReadU16(programCounter)
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return base &+ UInt16(register_x)
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case .Absolute_Y:
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let base = memReadU16(programCounter)
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return base &+ UInt16(register_y)
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case .Indirect_X:
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let base = memRead(programCounter)
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let ptr = UInt8(base) &+ register_x
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let lo = memRead(UInt16(ptr))
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let hi = memRead(UInt16(ptr &+ 1))
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return UInt16(hi) << 8 | UInt16(lo)
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case .Indirect_Y:
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let base = memRead(programCounter)
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let lo = memRead(UInt16(base))
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let hi = memRead(UInt16(base &+ 1))
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let deref_base = UInt16(hi) << 8 | UInt16(lo)
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let deref = deref_base &+ UInt16(register_y)
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return deref
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case .NoneAddressing:
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fatalError("mode \(mode) is not implemented")
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}
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}
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func memRead(_ addr: UInt16) -> UInt8 {
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memory[Int(addr)]
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}
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func memReadU16(_ addr: UInt16) -> UInt16 {
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let lo = UInt16(memRead(addr))
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let hi = UInt16(memRead(addr + 1))
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return (hi << 8) | lo
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}
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func memWriteU16(addr: UInt16, data: UInt16) {
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let hi = UInt8(data >> 8)
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let lo = UInt8(data & 0xff)
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self.memWrite(addr: addr, data: lo)
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self.memWrite(addr: addr + 1, data: hi)
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}
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func memWrite(addr: UInt16, data: UInt8) {
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memory[Int(addr)] = data
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}
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func reset() {
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register_a = 0
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register_x = 0
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register_y = 0
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status = 0
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programCounter = self.memReadU16(0xFFFC)
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}
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func loadAndRun(_ program: [UInt8]) {
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load(program)
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reset()
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run()
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}
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func load(_ program: [UInt8]) {
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memory[0x8000 ..< (0x8000 + program.count)] = program[0..<program.count]
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memWriteU16(addr: 0xFFFC, data: 0x8000)
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}
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func run() {
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let opcodes = OPCODES_MAP
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while true {
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let code = memRead(programCounter)
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programCounter += 1
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let programCounterState = programCounter
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guard let opcode = opcodes[code] else {fatalError("OpCode \(code) not recgonized!")}
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switch code {
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/// LDA
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case 0xa9, 0xa5, 0xb5, 0xad, 0xbd, 0xb9, 0xa1, 0xb1:
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lda(opcode.mode)
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/// STA
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case 0x85, 0x95, 0x8d, 0x9d, 0x99, 0x81, 0x91:
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sta(opcode.mode)
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/// TAX
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case 0xAA:
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tax()
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/// INX
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case 0xE8:
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inx()
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/// BRK
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case 0x00:
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return
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default: fatalError("TODO!")
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}
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if programCounterState == programCounter {
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programCounter += UInt16(opcode.len - 1)
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}
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}
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}
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func updateZeroAndNegativeFlags(_ result: UInt8) {
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if result == 0 {
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status = status | 0b0000_0010
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} else {
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status = status & 0b1111_1101
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}
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if result & 0b1000_0000 != 0 {
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status = status | 0b1000_0000
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} else {
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status = status & 0b0111_1111
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}
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}
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func lda(_ mode: AddressingMode) {
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let addr = getOpperandAddress(mode)
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let value = memRead(addr)
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register_a = value
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updateZeroAndNegativeFlags(register_a)
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}
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func tax() {
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register_x = register_a
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updateZeroAndNegativeFlags(register_x)
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}
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func inx() {
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register_x = register_x &+ 1
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updateZeroAndNegativeFlags(register_x)
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}
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func sta(_ mode: AddressingMode) {
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let addr = getOpperandAddress(mode)
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memWrite(addr: addr, data: register_a)
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}
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}
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7
Sources/main.swift
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7
Sources/main.swift
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// The Swift Programming Language
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// https://docs.swift.org/swift-book
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let cpu = CPU()
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let program: [UInt8] = [0xa9, 0xc0, 0xaa, 0xe8, 0x00]
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cpu.loadAndRun(program)
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print(cpu.status)
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38
Sources/opcodes.swift
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38
Sources/opcodes.swift
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struct OpCode {
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let code: UInt8
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let mnemonic: String
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let len: UInt8
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let cycles: UInt8
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let mode: AddressingMode
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}
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let CPU_OP_CODES: [OpCode] = [
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OpCode(code: 0x00, mnemonic: "BRK", len: 1, cycles: 7, mode: .NoneAddressing),
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OpCode(code: 0xaa, mnemonic: "TAX", len: 1, cycles: 2, mode: .NoneAddressing),
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OpCode(code: 0xe8, mnemonic: "INX", len: 1, cycles: 2, mode: .NoneAddressing),
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OpCode(code: 0xa9, mnemonic: "LDA", len: 2, cycles: 2, mode: .Immediate),
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OpCode(code: 0xa5, mnemonic: "LDA", len: 2, cycles: 3, mode: .ZeroPage),
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OpCode(code: 0xb5, mnemonic: "LDA", len: 2, cycles: 4, mode: .ZeroPage_X),
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OpCode(code: 0xad, mnemonic: "LDA", len: 3, cycles: 4, mode: .Absolute),
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OpCode(code: 0xbd, mnemonic: "LDA", len: 3, cycles: 4 /* +1 if page crossed */, mode: .Absolute_X),
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OpCode(code: 0xb9, mnemonic: "LDA", len: 3, cycles: 4 /* +1 if page crossed */, mode: .Absolute_Y),
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OpCode(code: 0xa1, mnemonic: "LDA", len: 2, cycles: 6, mode: .Indirect_X),
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OpCode(code: 0xb1, mnemonic: "LDA", len: 2, cycles: 5 /* +1 if page crossed */, mode: .Indirect_Y),
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OpCode(code: 0xa5, mnemonic: "STA", len: 2, cycles: 3, mode: .ZeroPage),
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OpCode(code: 0x95, mnemonic: "STA", len: 2, cycles: 4, mode: .ZeroPage_X),
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OpCode(code: 0x8d, mnemonic: "STA", len: 3, cycles: 4, mode: .Absolute),
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OpCode(code: 0x9d, mnemonic: "STA", len: 3, cycles: 5, mode: .Absolute_X),
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OpCode(code: 0x99, mnemonic: "STA", len: 3, cycles: 5, mode: .Absolute_Y),
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OpCode(code: 0x81, mnemonic: "STA", len: 2, cycles: 6, mode: .Indirect_X),
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OpCode(code: 0x91, mnemonic: "STA", len: 2, cycles: 6, mode: .Indirect_Y),
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]
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let OPCODES_MAP: [UInt8: OpCode] = {
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var map: [UInt8:OpCode] = [:]
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for cpuop in CPU_OP_CODES {
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map[cpuop.code] = cpuop
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}
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return map
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}()
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72
Tests/CPU.swift
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72
Tests/CPU.swift
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import XCTest
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@testable import SwiftNES
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class CPUTests: XCTestCase {
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func test_0xa9_lda_immediate_load_data() {
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let cpu = CPU()
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cpu.loadAndRun([0xa9, 0x05, 0x00])
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XCTAssertEqual(cpu.register_a, 0x05)
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XCTAssert(cpu.status & 0b0000_0010 == 0b00)
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XCTAssert(cpu.status & 0b1000_0000 == 0)
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}
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func test_lda_from_memory() {
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let cpu = CPU()
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cpu.memWrite(addr: 0x10, data: 0x55)
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cpu.loadAndRun([0xa5, 0x10, 0x00])
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XCTAssertEqual(cpu.register_a, 0x55)
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}
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func test_0xa9_lda_zero_flag() {
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let cpu = CPU()
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cpu.loadAndRun([0xa9, 0x00, 0x00])
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XCTAssert(cpu.status & 0b0000_0010 == 0b10)
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}
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func test_0xa9_lda_neg_flag() {
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let cpu = CPU()
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cpu.loadAndRun([0xa9, 0xFF, 0x00])
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XCTAssert(cpu.status & 0b1000_0000 == 0b1000_0000)
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}
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func test_0xaa_tax_move_a_to_x() {
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let cpu = CPU()
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cpu.load([0xaa, 0x00])
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cpu.reset()
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cpu.register_a = 10
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cpu.run()
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XCTAssertEqual(cpu.register_x, 10)
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}
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func test_0xe8_inx_incriment_x() {
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let cpu = CPU()
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cpu.load([0xe8, 0x00])
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cpu.reset()
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cpu.register_x = 10
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cpu.run()
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XCTAssertEqual(cpu.register_x, 11)
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}
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func test_5_ops_working_together() {
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let cpu = CPU()
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cpu.loadAndRun([0xa9, 0xc0, 0xaa, 0xe8, 0x00])
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XCTAssertEqual(cpu.register_x, 0xc1)
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}
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func test_inx_overflow() {
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let cpu = CPU()
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cpu.load([0xe8, 0xe8, 0x00])
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cpu.reset()
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cpu.register_x = 0xff
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cpu.run()
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XCTAssertEqual(cpu.register_x, 1)
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}
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}
|
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Block a user